FUNCTIONAL STRUCTURE FOR PRE-ADDER OF PARALLEL-SERIAL MULTIPLIER f(Σ) WITH MULTIPLICAND ARGUMENTS [m]f(2) AND MULTIPLIER ARGUMENTS [n]f(2) IN POSITION FORMAT (VERSIONS) Russian patent published in 2011 - IPC G06F7/505

Abstract RU 2422879 C1

FIELD: information technology.

SUBSTANCE: in one version, the functional structure is in form of two equivalent logic structures with conditional (j+1)-th and (j)-th bit using AND, OR and NOT logic elements to generate output arguments of the sum (S_j+1)_i and (S_j)_i, respectively.

EFFECT: faster pre-summation process in parallel-serial multiplier.

14 cl

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RU 2 422 879 C1

Authors

Petrenko Lev Petrovich

Dates

2011-06-27—Published

2010-03-04—Filed