FUNCTIONAL STRUCTURE OF ADDER f(Σ) OF ARBITRARY "i" BIT FOR LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF TERMS [n]f(2) and [m]f(2) USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2011 - IPC G06F7/50

Abstract RU 2429522 C1

FIELD: information technology.

SUBSTANCE: invention can be used when designing arithmetic units and performing arithmetic procedures of summation of positional arguments of analogue signals of terms [n_j]f(2ⁿ) and [m_i]f(2ⁿ) using the arithmetic axioms of the ternary number system f(+1,0,-1). The technical result of the invention is cutting the process cycle of converting arguments of terms [n_j]f(2ⁿ) and [m_i]f(2ⁿ) into the functional structure adder f_i(Σ) of the arbitrary "i" bit.

EFFECT: disclosed are various versions of the functional structure of an adder owing to introduction of additional logic functions and the disclosed functional relations enable to significantly increase speed of operation.

5 cl

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RU 2 429 522 C1

Authors

Petrenko Lev Petrovich

Dates

2011-09-20—Published

2010-05-25—Filed