FUNCTIONAL STRUCTURE OF A TRANSFORMER OF PRELIMINARY FA f [n]&[m](2) OF PARALLEL-SERIAL MULTIPLICATOR f (Σ) CONDITIONALLY, OF "i" DIGIT TO SUM UP OF POSITIONAL ADDITIVE OF SUMS [n]f(2) AND [m]f(2) OF PARTIAL PRODUCTS USING ARITHMETICAL AXIOMS OF TERNARY NOTATION f(+1, 0, -1) WITH THE FORMATION OF A RESULTING SUM [S]f(2) IN A POSITIONAL FORMAT Russian patent published in 2012 - IPC G06F7/505

Abstract RU 2443008 C1

FIELD: computational engineering.

SUBSTANCE: construction arithmetic of devices and introduction of different arithmetic procedures on arguments with positional symbolic structure of analog signals arguments [n_i]f(2ⁿ) and [m_i]f(2ⁿ) using arithmetical axioms of ternary notation f(+1, 0, -1).

EFFECT: increased the summing-up speed as the variants of the structure are realized using logical elements NOT, AND, OR, AND -NOT, OR-NOT.

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RU 2 443 008 C1

Authors

Petrenko Lev Petrovich

Dates

2012-02-20—Published

2010-07-22—Filed