FUNCTIONAL STRUCTURE OF ADDER f(Σ) OF CONDITIONAL "k" BIT OF PARALLEL-SERIAL MULTIPLIER f(Σ), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF INPUT STRUCTURES OF ARGUMENTS OF TERMS [S ]f(2) AND [S ]f(2) OF "COMPLEMENTARY CODE RU" POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d/dn → f(←↓) OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2013 - IPC G06F7/505

Abstract RU 2480817 C1

FIELD: information technology.

SUBSTANCE: invention relates to computer engineering and can be used when designing arithmetic units and performing arithmetic procedures of summation of positional arguments of analogue signals of terms [n_i]f(2ⁿ) and [m_i]f(2ⁿ) by applying the arithmetic axiom of the ternary number system f(+1,0,-1). The functional structure is realised using logic elements AND, OR.

EFFECT: faster operation.

1 cl

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RU 2 480 817 C1

Authors

Petrenko Lev Petrovich

Dates

2013-04-27—Published

2011-12-20—Filed