FIELD: information technology.
SUBSTANCE: method involves: mapping virtual containers (VC) in memory banks of synchronous dynamic random access memory SDRAM; writing write requests of the SDRAM of the virtual containers to the write request "first in first out" (FIFO) register of the corresponding virtual containers respectively; polling the write request FIFO register and the read request FIFO register of the virtual containers. The invention also provides an apparatus for improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer. The invention can reduce the wasteful overhead of the SDRAM, thereby improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer.
EFFECT: improved efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer.
16 cl, 6 dwg
