FUNCTIONAL SECOND INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER f(Σ) WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆t FOR ARGUMENTS OF TERMS [n]f(2) И [m]f(2) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM [S] OF SECOND TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2013 - IPC G06F7/50

Abstract RU 2480816 C1

FIELD: information technology.

SUBSTANCE: in one of the versions of the invention, the conditional j-th bit of the input functional structure of the adder is realised using logic elements NAND, NOR, AND, OR, NOT.

EFFECT: faster process of converting arguments in the input structure of the adder.

9 cl, 1 app

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RU 2 480 816 C1

Authors

Petrenko Lev Petrovich

Dates

2013-04-27—Published

2012-04-24—Filed