FUNCTIONAL OUTPUT STRUCTURE OF CONDITIONAL BIT "j" OF ADDER f(Σ) WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆t FOR ARGUMENTS OF TERMS OF INTERMEDIATE ARGUMENTS (S) "LEVEL 2" AND (S) "LEVEL 1" OF SECOND TERM AND INTERMEDIATE ARGUMENTS (S) "LEVEL 2" AND (S) "LEVEL 1" OF FIRST TERM OF "COMPLENTARY CODE RU" FORMAT WITH GENERATION OF RESULTANT ARGUMENTS OF SUM (S)f(2) "LEVEL 2" AND (S)f(2) "LEVEL 1" IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2013 - IPC G06F7/50

Abstract RU 2480814 C1

FIELD: information technology.

SUBSTANCE: in one of the versions of the invention, the conditional "j" bit of the output functional structure of the adder is realised using logic elements AND, OR.

EFFECT: faster process of converting arguments in the output structure of the adder.

5 cl

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RU 2 480 814 C1

Authors

Petrenko Lev Petrovich

Dates

2013-04-27—Published

2012-04-24—Filed