FIELD: physics, computer engineering.
SUBSTANCE: invention relates to digital computer engineering and is intended for planning the topology of logic integrated circuits when designing computer systems. The apparatus includes a device for searching for a lower estimate of arrangement in matrix systems with two-way information transmission and a device for planning the topology of logic integrated circuits, comprising a microprocessor, random-access memory, a memory direct access controller, a parallel port, a serial port, a PLD topology planning unit, an adjacency matrix and a circuit matrix of a unit for finding the minimum lower estimate, a search permutation unit, a unit for finding the minimum lower estimate, a unit for searching for the initial value of communication delay.
EFFECT: planning the topology of programmable logic devices (PLD) based on the criterion of minimising the intensity of interaction of processes and data.
2 cl, 18 dwg
