FIELD: physics.
SUBSTANCE: invention relates to digital computer engineering and is intended for simulating combinatorial tasks when designing computer systems. Device comprising a first and a second shift register, a permutation generating unit, a persistent memory unit, a best version storage unit, a switch, an ALU, an arc selection decoder, a reversible cell counter, a random-access memory unit, a topology counter, first and second distance meters, a multiplier, an adder, minimum link length register, a first comparison element, a subtractor, triggers for counting start, a topology setting mode and a link length register, a second comparison element, an arcs counter, arc lock decoder, arc number register, minimum weight register, graph electronic model, group of 1..n OR elements, group 1..m of AND elements, a minimum value unit containing the first RAM of circular cyclic system, RAM of cyclic fragment, SR mode trigger, multiplier, distance counter, subtracting counter.
EFFECT: wider range of technical means.
1 cl, 10 dwg
