FIELD: computer equipment.
SUBSTANCE: invention relates to digital computer engineering and is intended for simulating combinatorial tasks when designing computer systems. Device for assessing the degree of optimality of arrangement in multiprocessor cubic cyclic systems, comprising a first shift register, a second shift register, a unit for generating permutations (PGU), a constant memory unit, a best-of-memory storage unit (BMSU), a switch, ALU, arc selection decoder, reversible cell counter, random-access memory unit, first comparison element, count start trigger, mode trigger, arc counter, arc lock decoder, arc number register, a minimum weight register, an electronic graph model, a first to n-th OR group, a first to n-th AND group, a first and second AND element, a second OR element block, a third AND element, a first and a second delay element, the first unit of OR elements, besides, the PGU outputs are connected to the corresponding inputs of the constant memory unit and the corresponding inputs of the BMSU.
EFFECT: technical result consists in wider range of the same purpose tools.
1 cl, 10 dwg
