FIELD: digital computer engineering.
SUBSTANCE: technical result is achieved by a device which comprises a first shift register, a second shift register, a permutation generating unit (PGU), a persistent memory unit, a best option storage unit (BOSU), switch, ALU, arc selection decoder, reverse cell counter, random-access memory unit, topology counter, first and second distance meters, multiplier, adder, minimum links length register, a first comparison element, a subtractor, a count start trigger, a mode trigger, a topology setting flip flop, a link length register, a second comparison element, an arcs counter, an arc lock decoder, an arc number register, a minimum weight register, electronic graph model, group with 1st—nth OR element, group of 1st-to-mth AND element, first and second AND elements, second OR element block, third AND element, first and second univibrators, first, second and third delay elements, a first block of OR elements, an additionally introduced minimum value block comprising RAM unit 1, a RAM2, a first adder and a second adder.
EFFECT: technical result is to expand the field of use of the device by introducing means for assessing the degree of optimality of arrangement in multiprocessor cubic cyclic systems.
1 cl, 8 dwg
