APPARATUS FOR ANALYSING CHANNEL OVERLAPPING WHEN DEPLOYING PARALLEL SUBPROGRAMS IN MULTIPROCESSOR SYSTEMS Russian patent published in 2012 - IPC G06F17/00 

FIELD: information technology.

SUBSTANCE: apparatus has two shift registers, a shift generating unit, a read-only memory unit, a unit for storing the best version, a switch, an arithmetic logic unit (ALU), an arc selection decoder, a cell bidirectional counter, a random-access memory unit, a topology counter, two distance counters, a multiplier, an adder, a minimum connection length register, two comparator elements, a subtractor, a count onset flip-flop, a mode flip-flop, a topology setting flip-flop, a connection length register, an arc counter, an arc blocking decoder, an arc number register, a minimum weight register, an electronic graph model, a group of n OR elements, a group of m AND elements, two univibrators, three delay elements, a first unit of OR elements and a unit for analysing an overlapping list.

EFFECT: wider range of using the device owing to introduction of a means of analysing channel overlapping when deploying parallel subprograms in multiprocessor systems based on the criterion for minimising intensity of interaction of processes and data.

2 cl, 4 dwg