FIELD: computer equipment.
SUBSTANCE: invention relates to digital computer engineering and is intended for simulating combinatorial tasks when designing computer systems (CS). Disclosed is a device for assessing the degree of optimality of arrangement in multiprocessor cubic cyclic systems in the directed transmission of information, in which in comparison with the prototype there is a minimum value block containing RAM1, RAM2, a first adder, a second adder, a first reverse address counter of the row, a first reverse counter of the column address, a first intermediate register, a second intermediate register, a second reverse address counter of the row, a second reverse counter of the address of the column.
EFFECT: wider field of use of the device owing to the introduction of means for estimating the degree of optimality of arrangement in multiprocessor cubic cyclic systems when the information is sent through a criterion for minimizing the intensity of processes and data.
1 cl, 11 dwg
