METHOD FOR CODE CYCLE SYNCHRONISATION OF INFORMATION UNITS FOR FIXED LINK OPERATING SPEED RANGE Russian patent published in 2015 - IPC G06F11/00 H04L7/08 

FIELD: radio engineering, communication.

SUBSTANCE: method comprises first performing parallel processing of signals of a code sequence with N PCRU (phase correction and registration unit) devices; transmitting signals from each PCRU to inputs of corresponding N FS (frame synchroniser), which analyse the input sequence; in each FS, decoding PM (phase marker), based on which, in error-free words and words containing errors, the number of BCH code words is decoded and said numbers are recorded in corresponding counters; with each clock signal, increasing by one the numbers recorded in counters, the status of which is analysed at time instances corresponding to boundaries of codewords, determining the number of counters which, at the end of receiving the last message bit, are overfilled, and generating a FSS (frame synchronisation signal) for information units. The output of each PCRU is connected to the corresponding Data input of RAM. The FSS signal, generated in the FS, in which the frequency of clock signals matches the transmission speed of signals in the link, switches the corresponding RAM from Write mode to Read mode, wherein the data output of the RAM and the Information Attribute signal output is switched by a switch to the inputs of the decoder of a telecode communication receiver.

EFFECT: higher reliability of received information in high-noise level links.

3 cl