FIELD: radio engineering, communication.
SUBSTANCE: two-stage dynamic shift register consists of cells comprising two stages of MIS transistors with two MIS transistors in each stage, two clock buses, a power bus and a zero potential bus, wherein each cell includes an additional MIS transistor and a third clock bus, as well as connections thereof.
EFFECT: broader functional capabilities by providing reversibility of information shift within a shift register, minimising the occupied area of the IC chip, wider field of use by enabling two-way information transmission and stable operation of the shift register in conditions with significant parasitic capacitance of clock buses.
2 dwg
Title | Year | Author | Number |
---|---|---|---|
TWO-CYCLE DYNAMIC SHIFT REGISTER | 2014 |
|
RU2556437C1 |
SHIFT REGISTER | 2013 |
|
RU2522306C1 |
STORAGE ELEMENT FOR SHIFT REGISTER | 0 |
|
SU706880A1 |
SHIFT REGISTER | 2013 |
|
RU2527188C1 |
0 |
|
SU503295A1 | |
DYNAMIC SHIFT REGISTER | 2014 |
|
RU2542913C1 |
SHIFT REGISTER (VARIANTS) | 2013 |
|
RU2530271C1 |
PUSH-PULL SHIFT REGISTER | 2014 |
|
RU2549136C1 |
SHIFT REGISTER MEMORY CELL | 0 |
|
SU680055A2 |
STORAGE ELEMENT FOR DYNAMIC SHIFT REGISTER | 0 |
|
SU684617A1 |
Authors
Dates
2015-02-27—Published
2014-03-05—Filed