FIELD: electricity.
SUBSTANCE: two-cycle dynamic shift register comprises cells consisting of two inverters, each of them is assembled on the basis of load, switching and key MIS transistors of a p-type, of two clock buses, a supply bus and a zero potential bus, at that an additional MIS transistor and load MIS transistor of a p-type and the third clock bus are introduced to each cell.
EFFECT: expanded functionality due to ensured data shift reversibility inside the two-cycle dynamic shift register, minimised required space for IC chip, expanded scope of application due to the potential bidirectional transmission of data and stable operation of the device in conditions of the essential parasitic capacitance of clock buses.
2 dwg
Title | Year | Author | Number |
---|---|---|---|
PUSH-PULL SHIFT REGISTER | 2014 |
|
RU2549136C1 |
SHIFT REGISTER MEMORY CELL | 0 |
|
SU680055A2 |
TWO-STAGE DYNAMIC SHIFT REGISTER | 2014 |
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RU2542898C1 |
SHIFT REGISTER (VARIANTS) | 2013 |
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RU2530271C1 |
SHIFT REGISTER | 2013 |
|
RU2527188C1 |
SHIFT REGISTER | 2013 |
|
RU2522306C1 |
0 |
|
SU503295A1 | |
MEMORY CELL FOR SHIFT REGISTER | 0 |
|
SU570108A1 |
MEMORY REGISTER FOR SHIFT REGISTER | 0 |
|
SU1125655A1 |
DYNAMIC SHIFT REGISTER | 2014 |
|
RU2542913C1 |
Authors
Dates
2015-07-10—Published
2014-06-16—Filed