FIELD: physics, computer engineering.
SUBSTANCE: invention relates to computer engineering. Data processing device comprises a rearrangement means configured to rearrange mb code bits according to an allocation rule used to allocate code bits of a low density parity check (LDPC) code to symbol bits representing a symbol, and configured to set code bits after rearrangement as symbol bits when the code bits of the LDPC code, having a code length equal to N bits, are recorded in the column direction of a storage means configured to store code bits in the row direction and in the column direction, wherein the LDPC code has a code length N equal to 4320 bits, and a code rate equal to 1/2, wherein when m bits are four bits, the integer b is equal to two and four bits from said code bits are converted to one of 16 signal points, defined in 16-level quadrature amplitude modulation (16 QAM) system as one symbol, 4×2 code bits are grouped into three groups of code bits, and 4×2 symbol bits are grouped into two groups of symbol bits.
EFFECT: high error-resistance of the LDPC code.
20 cl, 158 dwg
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Authors
Dates
2016-02-10—Published
2011-09-09—Filed