FIELD: data processing.
SUBSTANCE: invention relates to devices and methods of data processing. For this purpose, when preset LDPC code (low density parity check), having length of code of 16,200 bits and code rate equal to 8/15, are displayed on 256 points signals at the same time (#i+1)-th bits, counted from the upper bit of 8×1 symbol bits, a (#i+1)th bit, counted from upper bit of 8×1 symbol bits one symbol are expressed as bit b#i and bit y#i respectively. At that demultiplexer is made with possibility of shifting to assign bit b0 as bit y2, bit b1 as bit y6, bit b2 as bit y1, bit b3 as bit y0, bit y4 as y7 bit, bit b5 as y5 bit, bit b6 as bit y3 and bit b7 as bit y4. This technology may be used, for example, in transmission systems, which transmit LDPC codes.
EFFECT: technical result is increase of resistance to data errors.
4 cl, 75 dwg
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Authors
Dates
2016-08-27—Published
2012-05-17—Filed