ARCHITECTURE OF ON-CHIP INTERCONNECTIONS Russian patent published in 2017 - IPC H04L12/933 

FIELD: physics.

SUBSTANCE: in one embodiment, the system comprises a plurality of pads formed on the semiconductor chip, at least, two of the plurality of pads have a plurality of cores; and a plurality of network switches formed on the semiconductor chip, which are connected to the plurality of pads, wherein the first network switch of the plurality of network switches comprises a plurality of output ports. The output ports of the first plurality of the plurality of output ports are designed to be connected to the corresponding network pad switch through the interconnection of type "point-point", and the output ports of the second plurality of output ports are designed to be connected to the corresponding network switches of the plurality of pads through the interconnection "point-multipoint", in which the width of the interconnection conductor "point-point" is greater than the width of the interconnection wire "point-multipoint".

EFFECT: increasing the network scalability with low latency and low power consumption.

18 cl, 9 dwg