FIELD: computer engineering.
SUBSTANCE: invention relates to computer equipment and, in particular, to vector processing in computing environment. Technical result is achieved by a process obtaining for execution machine instruction, containing operation code field for providing operation code which identifies operation of vector checksum type, first register field used to indicate first register, containing a first operand, second register field used to indicate second register, containing a second operand, and execution of machine instruction, which involves summation with each other of a set of elements of second operand to obtain a first result, including execution of one or more operations for addition with cyclic transfer, carried out on basis of addition with cyclic transfer and generating sum of addition of transfer from selected position of sum, if any, to selected position in selected element of first operand, and placing first result in selected element of first operand.
EFFECT: technical result consists in improvement of reliability of checksum.
20 cl, 32 dwg
