HIGH-SPEED DEVICE FOR GENERATING UNIQUE SEQUENCE USED FOR DEPERSONALIZING DATA Russian patent published in 2018 - IPC G09C1/00 G06F17/30 G06F21/62 

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering. High-speed device for generating a unique sequence for each subject of a personal data information system (PDIS) for depersonalizing data in PDIS, comprising clock generator 1, add-on unit 2 in which the bit sequence received over the Data + channel is complemented to a length multiple of 576 and outputted by 64-bit sequences, internal state generation unit 3, synchronization unit 4 in which the incoming fragments of the original data and the internal state are synchronized at the clock frequency, bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words, first pseudo-random permutation block 6 and second pseudo-random permutation block 7 in which the internal state bits are mixed, counter 8 of rectangular pulses and USB interface 9 in which the Data+ and Data- channels are informational, and + 5V and GRD are used to power the device, while the + 5V channel of USB interface 9 is connected to the input of clock generator 1, the input of rectangular pulse counter 8, the "in ready" input of complement unit 2, and the "in ready" input of internal state generation unit 3, the GRD channel of USB interface 9 is connected to second pseudo-random permutation unit 7, the Data+ USB interface 9 is connected to the input of add-in unit 2, the Data- USB interface channel 9 is connected to the output "H[0..511]" of second pseudo-random permutation unit 7, the "clk" output of clock generator 1 is connected to input "clk" of complement unit 2, input "clk" of internal state generating unit 3, input "clk" of synchronization unit 4, to the input "clk" of bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words, input "clk" of first pseudo-random permutation block 6 and the "clk" input of second pseudo-random permutation unit 7, the reset output of rectangular pulse counter 8 is connected to the reset input of add-in unit 2, the reset input of internal state generating unit 3, the reset input of bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words, the reset input of first pseudo-random permutation block 6 and the reset input of second pseudo-random permutation unit 7, the second input of square-wave counter 8 is connected to the output of second pseudo-random permutation unit 7, the "Mi[0..63]" output of supplementary unit 2 is connected to the input "Mi[0..63]" of synchronization unit 4 and the input "Mi[0..63]" of bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words, the output "S[0..1599]" of the internal state generating unit 3 is connected to the input "S[0..1599]" of synchronization unit 4, the output of synchronization unit 4 is connected to the input "S[0..1599]" of bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words, the output "S[0..1599]" bit-by-bit MODULO 2 SUM operation unit 5 with 64-bit words is connected to the input "S[0..1599]" of first pseudo-random permutation block 6, the output of first pseudo-random permutation block 6 is connected to the input "S[0..1599]" of second pseudo-random permutation block 7.

EFFECT: increased level of security of the personal data information system.

1 cl, 3 dwg, 3 tbl