FIELD: computer equipment.
SUBSTANCE: invention relates to computer technology and is intended for use in information processing systems. Apparatus comprises: N input characters D1, D2, …, DN by k digits, input data register, the first group of N OR elements, the first group of N AND elements, multi-output priority block, NOR element, second group of (N-1) OR elements, a group of N synchronous D flip-flops, a data switch block, an output buffer, an external synchronization input C, an external CLR input of the asynchronous setting to zero, external Q outputs of the device, an internal data line DD of N characters of k digits, an internal N bit line of M character mask, an internal N bit line of the trigger outputs T, and a group of W internal lines of high character pointers U1, U2, …, UW, wherein the data switch unit comprises W switches, and the multi-output priority block comprises W stages, each i-th stage comprising a group of (N-1-i) OR elements, a group of (N-i) inhibition elements AND with one inverse input and a group of (N-i) AND elements.
EFFECT: reduced time of data transfer and increased information capacity without loss of information.
1 cl, 3 dwg
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Authors
Dates
2018-11-16—Published
2017-12-11—Filed