FIELD: computer equipment.
SUBSTANCE: invention relates to computer engineering and is intended for use in information processing systems, and can also be used in data compression and decompression units without loss in systems for rational use of storage and transmission devices, processing data of physical experiments. Device comprises an input data register 2, a multi-output priority unit 3, a group of N data switches 41, 42, …, 4N, group of N registers 51, 52, …, 5N, output buffer 6, OR-NOT element 7, N groups 81, 82, …, 8N with k elements 2AND, register of mask 9, D-trigger 10, as well as input data bus 1, external synchronization input 11, external input of synchronous setting zero state 12, external outputs 13, internal data bus D, a first symbol mask bus M, a second QM symbol mask bus, a MS priority bus and w groups of N bit pointers of the leading unit S1, S2, …, Sw. Input data bus 1 contains a group of input bits of data ID, which consist of w symbols with k digits, and a group of input N bits of the IM symbol mask.
EFFECT: faster operation owing to reduction of input data capacity.
1 cl, 5 dwg
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Authors
Dates
2019-08-15—Published
2018-10-30—Filed