FIELD: computer technology.
SUBSTANCE: invention relates to the field of computer technology. The device contains N-bit external bus of input requests IZ and an external bus of outputs of priority indicators QU, an external operation enable input IE, an external clock input IC, an external setting input to the zero state IR and an external request flag QF, and also contains the first group of (N- 2) elements OR 13, 14, …, 1N, the first group of (N-1) elements AND 22, 23, …, 2N, the second group of (N-2) elements OR 33, 34, …, 3N, the third group of (N-1) elements OR 42, 43, …, 4N, the first group of (N-1) elements AND with inverse input 52, 53, …, 5N, the second group of N elements AND with inverse input 61, 62, …, 6N, fourth group of (N-1) OR elements 72, 73, …, 7N, OR element 8, AND element 9, first register 10, flip-flop 11, second register 12, internal N bit data bus BD, internal ( N-1) priority bit bus BU, internal enable flag FE, internal request flag FU, and internal zero flag FZ.
EFFECT: improving the accuracy of determining the priority pointer in peer-to-peer input requests based on circular arbitration.
1 cl, 2 dwg
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Authors
Dates
2022-12-13—Published
2022-03-09—Filed