FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering and is intended for use in information processing systems. Said result is achieved by the fact that device comprises N D1, D2, ..., DN input symbols by k bits connected to input data register 1, first group of N OR elements 21, 22, …, 2N, first group of N AND elements 31, 32, …, 3N, multi-output priority unit 4, NOR element 8, synchronous D-trigger 9, (N-W) bit register 10, data switches unit 11, output buffer 12, as well as external input C of synchronization 15, external input CLR of asynchronous setting to zero state 14, external outputs Q of device 16, as well as an internal data bus DD of N symbols with k digits, a group of W internal buses of high symbol indicators U1, U2, …, UW, internal N bit mask bus M and internal N bit bus BR, wherein the data switch unit includes W switches 111, 112, …, 11w, and multi-output priority unit includes W cascades 41, 42, …, 4w, wherein each i-th cascade 4i (i=1, 2, …, W, where W is the number of output symbols), contains a group of (N-1-i) OR elements 5i1, 5i2, …, 5i (N-i-1), group of (N-i) inhibition elements AND with one inverse input 6i1, 6i2, …, 6i (N-i) and group of (N-i) AND elements 7i1, 7i2, …, 7i (N-i).
EFFECT: wider range of tools for the same purpose.
1 cl, 3 dwg
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Authors
Dates
2020-01-14—Published
2019-05-07—Filed