FIELD: computer engineering.
SUBSTANCE: invention relates to computer technology and is intended for use in information processing systems. Device comprises N input symbols ID1, ID2, …, IDN by k digits connected to input data register 2, mask generator 3 containing a group of N OR elements, mask switch 4, mask register 5, a multi-output priority block 6 comprising w cascades, a data switch unit 7, containing w switches 71, 72, …, 7W, mask-data switch 8, output buffer 9, NOR element 10, synchronous D-flip-flop 11, external input C of synchronization 12, external input R of synchronous setting to zero state 13, external outputs Q of device 14, containing w symbols by k digits, as well as internal data bus DD of N symbols with k digits, internal N bit bus of mask of symbols M, group of w internal buses of indicators of upper characters U1, U2, …, Uw (where w is number of output symbols), internal bus of MS residual mask and flag of zero symbols (zero flag) FZ.
EFFECT: technical result consists in improvement of efficiency of packing data by reducing the required amount of memory for storing a sequence of groups of input binary symbols.
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Authors
Dates
2019-09-30—Published
2019-01-09—Filed