FIELD: computer equipment.
SUBSTANCE: invention relates to the field of computer equipment. Memory device is disclosed comprising: memory elements that store data and parity; a first decoder that, when data cleansing is performed, while no external access is performed to the memory device, it uses a syndrome generated from data and parity to correct the error of a maximum of N bits in the data block; and a second decoder, which, when data is read, uses the said syndrome, generated from data and parity, to correct the error from a maximum of M bits in the data block, moreover, M bits represents the number of bits less than N bits.
EFFECT: technical result is to increase the reliability of data storage while maintaining high speed memory system.
20 cl, 13 dwg
