FIELD: electricity.
SUBSTANCE: first device comprises word lines, connected to the memory cell array; second word lines connected to the spare area; The first line of a decoder configured to perform a selection of the first word lines on the basis of the row address; determination circuitry operable to determine whether or not a spare area replacing operation based on alternate-address included in the address line; and second lines of the decoder configured to perform a selection of the second word lines. Address lines include a first row address and a second row address input means in order of time-sharing. The first address line includes a full back-up address.
EFFECT: increase in speed of the memory device.
13 cl, 7 dwg
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