FIELD: electrical engineering.
SUBSTANCE: device comprises a main CPU and an additional CPU, connected to each other, and a main FPGA and an additional FPGA connected to each other, wherein both the basic FPGA and the additional FPGA are connected to the physical layer of the security device, and both the main CPU and the additional CPU are connected to the output of the status monitoring data of the protected device. Method comprises steps of: main CPU sends the processing result to the main FPGA, the additional CPU sends the processing result to the additional FPGA and the additional FPGA synchronizes current information with the primary FPGA after receiving information sent by the additional CPU; and, when the primary FPGA receives tripping information, the primary FPGAcompares current disconnection information received from the main CPU to match with the current disconnection information received from the additional FPGA, and, if they correspond to each other, the main FPGA sends information received from the main CPU to the security device, and otherwise discards information received from the main CPU.
EFFECT: technical result is improved ability of prevention of wrong operation of protective device and ensuring that device can not cause incorrect operation of primary device due to unknown failures, when there is failure of hardware device or single failure (SEU).
6 cl, 2 dwg
