FIELD: digital circuitry.
SUBSTANCE: invention relates to digital circuitry, automation and industrial electronics. Trigger synchronous D flip-flop incorporates two additional field transistors, seven resistors and the elements connection, the first additional transistor gate output forms relative to the "ground" synchronization trigger synchronization trigger C, one of the outputs of the first resistor is connected to the common drain of the first transistor and the gate of the third transistor, the second resistor is connected between the drain of the third transistor and the common lead of the source and the substrate of the fourth transistor, one of the leads of the third resistor is connected to the common lead of the first resistor and drain of the second transistor, one of the outputs of the fourth resistor is connected to the common output of the DC supply source, one of the outputs of the fifth resistor is connected to the "ground" output of the synchronous trigger output Q, one of the outputs of the sixth resistor is connected to the common output of the fourth resistor, one of the outputs of the seventh resistor is connected to the common drain terminal of the fourth transistor and the gate of the second additional transistor.
EFFECT: increased loading capacity of trigger synchronous D flip-flop on field-effect transistors.
1 cl, 1 dwg, 1 tbl
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