FIELD: data processing devices.
SUBSTANCE: device contains an external m-bit data input ID, an external (m+1)-bit input of a given pattern IG, an external v-bit input of the IK pattern width, where v=]log2(m+1)[(larger integer), group external data outputs QB, group of external outputs for the number of overlapping patterns QS, group of external outputs for the number of non-overlapping patterns QN, first RS start-stop trigger TSS 1, second D-trigger TR2 delay 2, CTG group counter 3, output buffer OB 4, decoder 5, group of m elements OR 61, 62,…, 6m, first group of (m+1) elements AND 71, 72,…, 7m+1, element AND 8, first element OR 9, second OR element 10, first units counting block 11, first adder 12, non-overlapping pattern register RN 13, first R1 data register 14, second R2 data register 15, group of m resolution blocks 161, 162,…, 16m, each of which contains (m+1) AND elements, a group of m comparators 171, 172,…, 17m, a group of m prohibition blocks 181, 182,…, 18m, each of which contains m elements AND-NOT, second group of 2m elements AND 191, 192,..., 192m, mask register RM 20, second unit counting block 21, second adder 22, overlapping pattern register RS 23.
EFFECT: providing the ability to specify the bit depth of a bit pattern and identifying overlapping and non-overlapping patterns containing specified groups of one and zero bits, and determining the number of identified patterns.
1 cl, 5 dwg
