FIELD: computer equipment.
SUBSTANCE: invention relates to pulse and computer equipment and is intended for construction of self-synchronizing trigger, register and computing devices, digital information processing systems. Technical task is solved by means of implementation of indicating of all trigger elements, namely: to circuit containing eight CMOS transistors of n-type, eight CMOS transistors of p-type, two paraphrase information inputs with zero spacer and two biphase information outputs, two AND-OR-NO elements are introduced, a hysteresis flip-flop and an indicator output, paraphrase inputs and biphase outputs of the RS-flip-flop are connected to the inputs of the AND-OR-NOT elements, the outputs of which are connected to the inputs of the hysteresis flip-flop, whose output is connected to the indicator output of the RS-flip-flop.
EFFECT: technical result consists in providing self-synchronous operation of RS-flip-flop with zero spacer and prevention of its switching to incorrect operating state due to single logical failure.
1 cl, 1 dwg
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