FIELD: data processing.
SUBSTANCE: invention is intended for construction of fault-tolerant self-synchronizing trigger, register and computing devices, digital information processing systems. In a trigger circuit comprising eight n-type CMOS transistors, eight p-type CMOS transistors, two paraphrase data inputs with a single spacer and two biphase information outputs, two OR-AND-NOR elements are introduced, hysteresis trigger and indicator output, paraphrase inputs and biphase outputs of RS trigger are connected to inputs of OR-AND-NOT elements, outputs of which are connected to inputs of hysteresis trigger, whose output is connected to indicator output of RS-trigger.
EFFECT: technical result consists in providing self-synchronized operation of trigger by implementation of indicatability of all its elements.
1 cl, 1 dwg
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