FIELD: physics.
SUBSTANCE: invention relates to computer engineering. Technical result is achieved due to that the group structure counter with preservation of the number of units in the groups contains external input N bit data bus DI, external output N bit bus QO, group of G group counters 11, 12, …, 1G, first group of G elements AND 21, 22, …, 2G, group of G elements OR 31, 32, …, 3G, inter-group hyphenation unit 4, external clock input CLK, external input G bit buses for enabling loading into EL groups, parallel counting of EP groups and consecutive counting of EC groups, external output of CO transfer. Each of group counters 1i (where i = 1, …, G) consists of (Ki) digits (where N = K1 + K2 +…+ KG) and contains (Ki) D-flip-flops 51, 52, …, 5(Ki), transferring generator 6, group of (Ki) code generators with preservation of number of units 71, 72, …, 7(Ki), group of (Ki) MX multiplexers 81, 82, …, 8(Ki), OR element 9 and internal (Ki) bit bus of QT outputs of flip-flops.
EFFECT: technical result is reduction of hardware costs, faster operation and possibility of storing a given number of units in sets of consecutive states of the counter.
1 cl, 1 tbl, 3 dwg
Authors
Dates
2020-11-19—Published
2020-03-17—Filed