FIELD: computer technology.
SUBSTANCE: device contains: M bits D0, …, D(M-l) of a group of input data from an N-bit binary number, output (n+1) and n-bit buses of the QD range width, the numbers of the lowest single digit QL and the number of single bits QU, respectively, the output flag of the single bits QF1, start-stop triggers TSS and single bits TU, two elements AND, group counter, element OR, priority encoders of the highest and lowest single digits, unit counting module, output registers of the number of the highest RGM single bit and RGL low single bit numbers, SMS difference adders and SMU single bits, the INC incrementor, the output register of the number of single bits, the external inputs for stopping STOP and starting START, clock signals WITH and asynchronous setting to the zero state of CLR, the internal flag of single bits in the FU group, the internal m-bit buses of the numbers of the highest and lowest single bits in the M-bit group, the internal (n-m) and (m+1) bit bus numbers of the BD group and the number of single bits in the AU group, respectively.
EFFECT: ability to identify the boundaries of the range of single bits, estimate the width of the range.
1 cl, 3 dwg
