FIELD: computer equipment.
SUBSTANCE: invention relates to computer engineering. Device comprises N digits of input binary number D1, D2, …, DN, which are divided into N/2 groups by two bits in a group, Z steps of elements units, where Z=] log2N[(] [– a larger integer), and a difference code generation unit, the first stage comprising N/2 units of elements 11, 12, …, 1N/2 first type, and each i-th stage, starting from the second stage to the Z-th stage, contains by N/2i blocks of elements 2ij of the second type, where i=2, 3, …, Z, j=1, 2, N/2i, each of N/2 blocks of elements 11, 12, …, 1N/2 first type first stage comprises first "EQUIVALENCE" element, first AND element with one inverse input 4, "XOR" element, second AND element and third AND element with inverse inputs, each unit of elements 2ij second type second, third,…, Z-th stage contains third adder SM, subtractor SB, a control unit, a first group of AND elements, a second group of AND elements, a first group of OR elements, an OR element, a second adder SM2, a first adder SM1, a third group of AND elements, a first group of MX multiplexers, a first CMP comparator, a second group of MX multiplexers, a second CMP comparator, an eighth AND element, a third group of MX multiplexers, a third CMP comparator, a fourth group of MX multiplexers, a fourth CMR comparator, a ninth AND element with one inverse input, a fifth group of multiplexers MX and a fourth adder SM, a unit for generating a difference code comprises a fifth adder SM with an inverse group of inputs, a second group of elements OR, a ninth group of elements AND and a group of elements "XOR".
EFFECT: technical result consists in enabling identification of groups of single and zero bits in binary numbers, determination of the number of groups, as well as detection of maximum groups of single and zero bits and simple increase in the width of input information.
1 cl, 4 dwg, 2 tbl
