INTEGRAL ELECTRONIC CMOS SYNAPSE Russian patent published in 2023 - IPC G06N3/63 H01L27/92 B82Y40/00 

FIELD: neuromorphic electronics.

SUBSTANCE: promising elemental base of neuromorphic electronics. An integral electronic CMOS synapse containing MOS transistors with hole conductivity channels that determine the synaptic weight, the number of which is M=log₂N, where N is the number of conductivity levels of the integral electronic synapse, and the channel widths Wi_i of MOS transistors that determine the synaptic weight, are interconnected by the relation W_i =2W_i-1, where i is the serial number of the MOS transistor (i=0, 1,… , M-1); M key MOS transistors with hole conduction channels. The device contains a CMOS inverter based on a complementary pair of MOS transistors with electron and hole conductivity, the gate contacts of which are connected and form the input line of the electronic synapse, and the drain contacts are connected and form the output line of the CMOS inverter. The channel width of the i-th key MOS transistor with hole conductivity of the channel is equal to the channel width of the i-th MOS transistor with hole conductivity of the channel that determines the synaptic weight, for all i=0, 1,… ,M-1, the source contact of the MOS transistor with hole conduction of CMOS inverter and the source contacts of all the key hole conduction MOS transistors of the channels are connected to the power line. The source contact of the MOS transistor with the electronic conductivity of the CMOS inverter is connected to the constant bias voltage line, the drain contact of the i-th key MOS transistor with the hole conductivity of the channel is connected to the source contact of the i-th key MOS transistor with the hole conductivity of the channel that determines the synaptic weight, for all i=0, 1,… ,M-1, the gate contacts of all hole-conducting channel MOS transistors that determine the synaptic weight are connected to the output line of the CMOS inverter. The drain contacts of all MOS transistors with hole conduction channels that determine the synaptic weight are connected to the output line of the electronic synapse, the gate contacts of all key MOS transistors with hole conduction channels form an M-bit digital control bus of the electronic synapse.

EFFECT: reducing the area occupied by an electronic synapse on a chip, reducing the input capacitance of the electronic synapse, reducing power consumption and reducing the error in setting the conductivity level of the electronic synapse.

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