PROGRAMMABLE LOGIC DEVICE Russian patent published in 2024 - IPC G06F7/57 H03K19/173 

FIELD: computer technology.

SUBSTANCE: invention can be used to calculate logical functions in programmable logic integrated circuits (FPLIC). The result is achieved by introducing a subgroup of k-1 additional tuning inverters for each of the 2ⁿ tuning inverters of the group of 2ⁿ tuning inverters, a subgroup of k-1 additional tuning inputs for each input from the group of tuning inputs, k additional variable inputs, 2ⁿ additional groups of transmitting transistors k transistors per group, k additional input variable inverters and 2ⁿ additional outputs.

EFFECT: reducing the time delay when implementing logical functions of a large number of variables in the FPLIC, without increasing the complexity in the number of transistors.

1 cl, 4 tbl, 3 dwg