FIELD: electrical engineering. SUBSTANCE: device has in each phase two principal thyristors 3, 4, 9, 10, 15, 16 each connected in series with proper load 1, 2, 7, 8, 13, 14. Anode and cathode of supplementary pair of thyristors 5, 6, 11, 12, 17, 18 are linked to anode and cathode of principal thyristors 3, 4, 9, 10, 15, 16 and to input lead-in. Cathodes of first and anode of second thyristors of supplementary pair are tied together and to lead-out of common point for connection of load. With consumption of power P≅1/m control pulses are fed to principal thyristors and when power P>1/m principal thyristors remain open and control pulses are sent to supplementary thyristors. EFFECT: enhanced control efficiency. 2 cl, 3 dwg
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Authors
Dates
1995-02-27—Published
1990-10-25—Filed