METHOD OF MAKING SELF-ALIGNED TRANSISTOR STRUCTURES Russian patent published in 2009 - IPC H01L21/8222 

FIELD: physics; radio.

SUBSTANCE: invention relates to microelectronics. The method of making self-aligned transistor structures involves formation of a buried layer of second type conductivity in a semiconductor substrate of first type conductivity, formation an epitaxial layer of second type conductivity on the semiconductor substrate, formation of a first dielectric, doping the epitaxial layer through the first dielectric with impurities of first type conductivity, formation of a second dielectric layer, opening windows in the first and second dielectrics at the site of the future collector contact to the buried layer, at the site of the future contact to the inactive region of the base, at the site of the future emitter region, formation of a third separating dielectric on vertical walls, formation of screening layers in windows, formation of a fourth dielectric, opening windows in the first, second and fourth dielectrics under a deep insulating region and a window in the fourth dielectric over the screening layer lying at the site of the future collector contact to the buried layer, formation of an etching slit in the window of the epitaxial, buried layers and partially of the substrate under the insulating region, and in the window at the site of the future collector contact to the buried layer, by etching the screening and epitaxial layers, formation of a first dielectric in the slit, formation of opposite-channel regions at the bottom of the slit, formation of a third dielectric in the slits, local etching of the first and third dielectrics with the bottom of the slits under the contact to the substrate and collector contact to the buried layer, filling the slits with polysilicon, planarisation of polysilicon to the fourth dielectric lying on the horizontal surface of the substrate, local doping of the polysilicon contact to the substrate with an impurity of first type conductivity, local doping of the polysilicon collector contact to the buried layer with an impurity of second type conductivity, formation of a dielectric on the polysilicon, local etching of the fourth dielectric on the horizontal surface of the substrate, local removal of the fifth dielectric on the polysilicon at the site of the collector contact to the buried layer and the contact to the substrate, local doping with an impurity of first type conductivity of the polysilicon contact to the substrate and screening layer at the site of the contact to the inactive region of the base, local doping with an impurity of second type conductivity of the polysilicon collector contact to the buried layer and screening layer at the site of the emitter region, thermal annealing of the structure to form regions of the structure, wiring the structure with polycide of a high-melting metal.

EFFECT: higher packing density of transistor structures due to self alignment of the regions of the transistor structure and self alignment of insulating regions with the contact to the substrate and self alignment of the latter with regions of the transistor structure; completely self-aligned technology also increases reproducibility of device parametres.

3 cl, 8 dwg, 1 ex