VOLTAGE MEASUREMENT TECHNIQUE FOR PLANAR SEMICONDUCTOR REGIONS OF METAL-INSULATOR- SEMICONDUCTOR STRUCTURES Russian patent published in 1999 - IPC

FIELD: semiconductor engineering. SUBSTANCE: bias voltage U_bias and depleting voltage pulses U₁ and U₂≥ 2U₁ are applied to MIS structure, pulses U₁ and U₂ are timed, and difference in their amplitude is used to obtain third pulse U₃; integrated values of capacitors C₁, C₂ and C₃, respectively, are measured across them, and voltage across planar areas of MIS structures are found using U_bias in case 1/C₁+1/C₂= 1/C₃. condition is satisfied. In recording U_bias= U_FB, U_FB is determined accurate to 1.0% within comprehensive range of doping impurity concentrations in semiconductor (N ~ 10¹¹÷ 10¹⁸ cm^-3), MIS structure insulator thicknesses (d ~ 0,01 ÷ 1 mcm), and surface status densities at insulator-semiconductor interface (N ~ 10¹¹ eV^-1 cm^-2). Standard radio measuring equipment is used for the purpose. Capacitance of semiconductor spatial charge area is measured in mode of planar areas so as to determine semiconductor doping level by using known equation. EFFECT: facilitated procedure and improved measurement accuracy. 2 dwg, 2 tbl