FIELD: computer engineering. SUBSTANCE: device has buffer memory unit 1, gates M11 and M12 of output buffer unit 5, gates M7 and M8 of preliminary charge unit 9, buffer gates M7 and M8, ND gate and ND-2-NAND gate, NOT gates 17 and 18, preliminary charge control unit 10. Buffer memory units 11 and 12, level generators 2 and 3 and design of unit 10, which has permission pulse generator 6 and control pulse generator 7, are introduced to accomplish the goal of invention. EFFECT: increased speed, decreased noise during switches. 2 cl, 2 dwg
