FIELD: computer engineering; data processing devices. SUBSTANCE: device has N series-connected dynamic CMOS gates. Synchronizing input of each conveyer stage is connected to one of logic gates and to state recovery input of first dynamic CMOS gate of this stage; state recovery input of each CMOS gate except for first one is connected to one of logic inputs of this gate the latter being connected to logic output of preceding gate. EFFECT: enhanced speed and functional reliability in wide range of time spaces. 6 cl, 7 dwg
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Authors
Dates
2001-11-10—Published
2000-12-29—Filed