FIELD: integrated transistor/memory structures.
SUBSTANCE: proposed integrated transistor/memory structures have one or more semiconductor layers, two or more electrode layers, as well as memory material contacting electrodes residing in mentioned electrode layers. At least one semiconductor layer and at least two electrode layers form transistor structures. Electrodes of first electrode layer form pairs of source and drain electrodes and those of adjacent second electrode layer form gate electrodes of mentioned structures. Source and drain electrodes of single transistor/memory structure are separated by narrow groove deep enough to reach semiconductor layer. Transistor channel of super-short length L is provided in semiconductor layer under groove; source and drain regions are formed under source and drain electrodes either side of transistor channel. Memory material fills up groove and is held in contact with transistor electrodes. Transistor channel length L corresponds in this circuit arrangement to groove width and its width W, to that of gate electrode, L being a fraction of W. Three memory locations are formed within memory material and disposed, respectively, between source electrode and gate electrode, between drain electrode and gate electrode, as well as in groove between source and drain electrodes. Array of integrated transistor/memory structures is also given in invention specification.
EFFECT: ability of integrating nonvolatile memory and high-speed transistor circuits in proposed structures.
25 cl, 10 dwg
