FIELD: computer engineering; reception of differential two-level coded signal of sequential self-synchronizing code with conversion to two-digit digital signal and further noise-resistant execution of full synchronization function for this signal using input continuous timing pulse sequence.
SUBSTANCE: device consists of detector-transducer (6), inputs (19,20) of first and second components of differential two-level coded signal, triggers (1-5), NAND elements (7,8), AND (21-24), OR (15-17), negative OR (11-13), XOR elements (9-10), asynchronous delay component (14), clocked delay components (27), clock input (18), and four outputs.
EFFECT: increased noise immunity due to noise-resistant forming of output synchronized signal and outputs clock signals of bit synchronization, pause start and pause with obstructing filtration, synchronization of two-digit digital signal of two-level code 1B2B, as noise, with duration of signal changes not exceeding the threshold duration P*Tic for P≥2, where P - threshold number, Tic - duration of clock pulse period.
1 dwg
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|---|---|---|---|
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| DEVICE FOR CLOCK SYNCHRONIZATION OF DIGITAL SIGNAL | 2005 | 
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| DIGITAL SIGNAL CLOCK SYNCHRONIZATION DEVICE | 2005 | 
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 | RU2220502C2 | 
Authors
Dates
2006-12-27—Published
2005-05-27—Filed