FIELD: information technologies.
SUBSTANCE: device contains AND-NOT gates (1, 2), with outputs (13, 14) connected to locks of r-type inverting gate (IG) (3) logical transistors (T) (7,8) which are included in a parallel way between the power supply bus (12) and device output (18), thereat the AND-NOT gate (1,2) contains a key circuit (6) on T n-type and connected between the power supply bus (12) and output of the given unit, preconduction T types (4) of p-type and T (5) of n-type with locks connected to the clock bus (11) and the antiphase clock bus (15), and IG (3) contains connected between the zero bus (19) and device output (18) clock T (9) of p-type and T (10) of n-type with locks connected to the clock (11) and the antiphase clock (15) buses. Introduction of preconduction T of n-type with antiphase clocking leads to compensation of additional charges on output capacities during operation of clock signals fronts. Currents are compensated through transit capacities of preconduction T of n- and p-types and clock T of n-and p-types and negative influence of clock signal fronts on switching process is completely eliminated.
EFFECT: increase of operation speed.
1 dwg
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