FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used for implementation of cascade logic devices of conveyor type. Technical result is achieved due to that a dynamic AND-OR logical element has clock 1, precharge 2 and logic 3 p-type transistors, n-type clock 4 transistor and a logic unit 5, comprising switch circuits 6, each of which consists of series-connected n-type transistors, logical inputs 7 of element, output 8 of logical unit 5, clock bus 9, which is also connected to gate of n-type clock 4 transistor, output 10 of element and antiphase clock bus 11.
EFFECT: technical result is simple design of dynamic logic element.
1 cl, 1 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| CLOCKED AND-OR GATE | 2012 |
|
RU2515702C1 |
| CLOCKED LOGIC ELEMENT | 2010 |
|
RU2427073C1 |
| PARAPHASE LOGICAL ELEMENT | 2009 |
|
RU2393631C1 |
| CLOCKED MULTI-INPUT AND-ELEMENT | 2009 |
|
RU2412542C1 |
| PARAPHASE LOGICAL ELEMENT | 2014 |
|
RU2542660C1 |
| CLOCKED LOGICAL ELEMENT AND-OR ON CMDS-TRANSISTORS | 2008 |
|
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| MULTI-INPUT LOGICAL "AND" ELEMENT ON CMOS TRANSISTORS | 2006 |
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| AND-OR GATE | 2007 |
|
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| PARA-PHASE LOGICAL ELEMENT BASED ON SHORT-CHANNEL MIS TRANSISTORS | 2003 |
|
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| PARAPHASAL LOGIC ELEMENT BUILT AROUND MIS TRANSISTORS | 1995 |
|
RU2107387C1 |
