FIELD: information technology.
SUBSTANCE: device has a clock CMIS inverter and, in each stage, two n-type reset transistors, two CMIS inverters, a delay element and a logic unit, key circuits made from series-connected n-type transistors, power and earthing buses. The delay element has two inverting elements, each having a p-type transistor and an n-type transistor. The CMIS inverters are connected in a flip-flop circuit.
EFFECT: faster operation of the device.
2 dwg
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