DEVICE FOR PARALLEL BOOLEAN SUMMATION OF ANALOGUE SIGNALS OF TERMS EQUIVALENT TO BINARY NUMBER SYSTEM Russian patent published in 2009 - IPC G06F7/50

Abstract RU 2363978 C2

FIELD: information technology.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic elements and executing arithmetic operations, particularly summation and subtraction, in positional-sign codes. Each bit of the adder contains four OR elements, two AND elements, three NOT elements and is made in form of two channels - a channel for generating positive sum and a channel for generating conditionally negative sum.

EFFECT: faster operation.

5 dwg

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RU 2 363 978 C2

Authors

Petrenko Lev Petrovich

Dates

2009-08-10—Published

2006-12-15—Filed