METHOD PARALLEL BOOLEAN SUMMATION OF ANALOGUE SIGNALS OF COMPONENTS EQUIVALENT TO BINARY NUMBER SYSTEM AND DEVICE TO THIS END Russian patent published in 2009 - IPC G06F7/50

Abstract RU 2362205 C2

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices and carrying out arithmetic operations, particularly summation and subtraction, in position-sign codes. Each bit of the adder has three OR elements, three AND elements, two NOT elements and is made in form of two channels - channel for generating positive sum and channel for generating conditionally negative sum.

EFFECT: faster operation.

2 cl, 5 dwg

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RU 2 362 205 C2

Authors

Petrenko Lev Petrovich

Dates

2009-07-20—Published

2006-12-15—Filed